How To Register Dynamic Array In Uvm

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures.

This post is the first in a series of tutorials about packing and unpacking in SystemVerilog.

The commodity's sections are:

• Introduction
• 1. Pack bytes into an int
• one.1 Byte variables to an int
• 1.2 Assortment of bytes to an int
• 2. Reverse the elements of a byte array and pack them into an int
• 3. Contrary the bits in a byte
• 4. Opposite the nibbles in a byte
• v. Reverse the bits of an assortment and pack them into a shortint
• 6. Avant-garde packing
• References

Introduction

When doing packing/unpacking operations in SystemVerilog, a uncomplicated bit-stream cast is often enough:

          typedef struct {   bit [7:0] address;   bit [7:0] payload[ii]; } bundle;  typedef bit [7:0] data_stream[$]; // ... parcel      pkt; data_stream stream; // ... stream = { stream, data_stream'(pkt) };                  

For extra flexibility, streaming operators can be used in the cases where the bit ordering is important or a simple scrap-stream cast is not sufficient..

There are two streaming operators, {>>{}} and {<<{}}, which operate on data blocks (or slices). By default, slices have the size 1, but the slice size can exist inverse according to the needs. Using {>>{}} will crusade the data blocks to be streamed from left to right, while {<<{}} will stream the data blocks from right to left.

Because an epitome is worth a thousand words, I'll apply graphics to bear witness how to utilize the streaming operators and how the individual bits are affected by the stream operators.

1. Pack bytes into an int

1.i Byte variables to an int

When we need to pack several variables into a single variable, nosotros tin use the left-to-right streaming operator ( {>>{}} ).

          module example_1_1;   initial begin     static byte a     = viii'h8C;     static byte b     = 8'h00;     static byte c     = 8'hA4;     static byte d     = 8'hFF;     static int  value = {>>{a, b, c, d}};      $display("value = 0x%h", value);   end endmodule                  

Specifying a slice size for left-to-right streaming operator ( {>>{}} ) has the same effect every bit using the default piece size of ane. This means that {>>{}} is the aforementioned as {>>4{}}, {>>8{}}, or whatever other value.

1.2 Array of bytes to an int

Packing an assortment of bytes into a unmarried variable is merely as like shooting fish in a barrel:

          module example_1_2;   initial begin     static bit [7:0] array[four] = '{ 8'h8C, 8'h00, eight'hA4, eight'hFF };     static int       value    = {>>{array}};      $display("value = 0x%h", value);   terminate endmodule                  

ii. Opposite the elements of a byte array and pack them into an int

We can reverse the order of an array'southward elements and and so pack them into a single value in the post-obit manner:

          module example_2;   initial begin     static scrap [vii:0] array[4] = '{ viii'h8C, 8'h00, 8'hA4, eight'hFF };     static int       value    = {<<eight{array}};      $brandish("value = 0x%h", value);   stop endmodule                  

If the slice size would be 16 instead of eight, the output value would be 0xA4FF_8C00.

iii. Opposite the bits in a byte

Beneath is an easy mode to contrary the order of the $.25 within a byte. The slice size defaults to 1 if information technology is not specified. The slice size is a resolution/granularity like concept.

          module example_3;   initial begin     static bit [7:0] value_a = 8'h8C;     static bit [7:0] value_b = {<<{value_a}};      $display("value_b = 0x%h", value_b);   end endmodule                  

If the slice size would be 2 instead of ane, the bits would be reversed in groups of 2, leading to an output value of eight'b00_11_00_10.

If the slice size would exist 3, groups of 3 bits would be created starting from the least significant 3 bits. Since we have an 8-chip input value, the last (leftmost) group will incorporate the remaining ii bits. No padding or truncation is performed. The bit grouping reversing would then be performed, leading to the output value viii'b100_001_10.

4. Reverse the nibbles in a byte

A byte contains a low nibble and a high nibble. The lodge of the nibbles inside the byte tin can be reversed using the correct-to-left streaming operator with a slice size of four:

          module example_4;   initial begin     static bit [vii:0] value_a = 8'h8C;     static bit [seven:0] value_b = {<<4{value_a}};      $display("value_b = 0x%h", value_b);   end endmodule                  

v. Opposite the bits of an array and pack them into a shortint

Reversing the elements of an array and, at the same time, the $.25 of each element of the assortment is easily achievable using the correct-to-left streaming operator:

          module example_5;   initial brainstorm     static bit [7:0] array[2] = '{ 8'h8C, viii'hA4 };     static shortint  value    = {<<{assortment}};      $display("value = 0x%h", value);   stop endmodule                  

6. Advanced packing

In this terminal instance, we'll take an assortment of 2-scrap values and pack it into a structure. The ordering scheme used for the values in the assortment is little endian. Nosotros tin can accomplish this past taking the result of a right-to-left streaming operator with a piece size of 2, and feeding it equally input to another right-to-left streaming operator with a piece size of iv:

          module example_6;   typedef struct {     bit [three:0] addr;     bit [iii:0] information;   } packet_t;    initial begin     static bit [one:0] array[] = '{ 2'b10, 2'b01, two'b11, 2'b00 };     static packet_t  packet  = {<<4{ {<<2{array}} }};      $display("package addr = %b", parcel.addr);     $brandish("bundle data = %b", bundle.data);   end endmodule                  

If the ordering scheme is big endian, the packing can be performed with a single right-to-left streaming operator ( {>>{}} ), using the default slice size.

References

The above diagrams have been created using an open source design tool called Inkscape. Stay tuned for more than packing/unpacking tutorials (Unpacking using streaming operators and UVM pack/unpack).

Source: https://www.amiq.com/consulting/2017/05/29/how-to-pack-data-using-systemverilog-streaming-operators/

Posted by: lynchthouthe1935.blogspot.com

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